********** Mapped Logic ********** |
XLXI_1/T11/XLXI_1/T11_D2 <= (ct(9) AND ct(10) AND XLXI_1/T9/XLXI_1/T9_D2); |
XLXI_1/T13/XLXI_1/T13_D2 <= (ct(12) AND ct(11) AND XLXI_1/T11/XLXI_1/T11_D2); |
XLXI_1/T15/XLXI_1/T15_D2 <= (ct(13) AND ct(14) AND XLXI_1/T13/XLXI_1/T13_D2); |
XLXI_1/T3/XLXI_1/T3_D2 <= (ct(0) AND ct(1) AND ct(2)); |
XLXI_1/T5/XLXI_1/T5_D2 <= (ct(4) AND ct(3) AND XLXI_1/T3/XLXI_1/T3_D2); |
XLXI_1/T7/XLXI_1/T7_D2 <= (ct(5) AND ct(6) AND XLXI_1/T5/XLXI_1/T5_D2); |
XLXI_1/T9/XLXI_1/T9_D2 <= (ct(8) AND ct(7) AND XLXI_1/T7/XLXI_1/T7_D2); |
FDCPE_XLXN_260: FDCPE port map (XLXN_26(0),spi(0),spi_clk,'0','0',XLXN_26_CE(0));
XLXN_26_CE(0) <= (NOT spi_ce AND NOT spi(10) AND NOT spi(8) AND NOT spi(9) AND NOT spi(11)); |
FDCPE_XLXN_261: FDCPE port map (XLXN_26(1),spi(1),spi_clk,'0','0',XLXN_26_CE(1));
XLXN_26_CE(1) <= (NOT spi_ce AND NOT spi(10) AND NOT spi(8) AND NOT spi(9) AND NOT spi(11)); |
FDCPE_XLXN_262: FDCPE port map (XLXN_26(2),spi(2),spi_clk,'0','0',XLXN_26_CE(2));
XLXN_26_CE(2) <= (NOT spi_ce AND NOT spi(10) AND NOT spi(8) AND NOT spi(9) AND NOT spi(11)); |
FDCPE_XLXN_263: FDCPE port map (XLXN_26(3),spi(3),spi_clk,'0','0',XLXN_26_CE(3));
XLXN_26_CE(3) <= (NOT spi_ce AND NOT spi(10) AND NOT spi(8) AND NOT spi(9) AND NOT spi(11)); |
FDCPE_XLXN_264: FDCPE port map (XLXN_26(4),spi(4),spi_clk,'0','0',XLXN_26_CE(4));
XLXN_26_CE(4) <= (NOT spi_ce AND NOT spi(10) AND NOT spi(8) AND NOT spi(9) AND NOT spi(11)); |
FDCPE_XLXN_265: FDCPE port map (XLXN_26(5),spi(5),spi_clk,'0','0',XLXN_26_CE(5));
XLXN_26_CE(5) <= (NOT spi_ce AND NOT spi(10) AND NOT spi(8) AND NOT spi(9) AND NOT spi(11)); |
FDCPE_XLXN_266: FDCPE port map (XLXN_26(6),spi(6),spi_clk,'0','0',XLXN_26_CE(6));
XLXN_26_CE(6) <= (NOT spi_ce AND NOT spi(10) AND NOT spi(8) AND NOT spi(9) AND NOT spi(11)); |
FDCPE_XLXN_267: FDCPE port map (XLXN_26(7),spi(7),spi_clk,'0','0',XLXN_26_CE(7));
XLXN_26_CE(7) <= (NOT spi_ce AND NOT spi(10) AND NOT spi(8) AND NOT spi(9) AND NOT spi(11)); |
FDCPE_ct0: FDCPE port map (ct(0),ct_D(0),clk,'0','0');
ct_D(0) <= (NOT ct(0) AND NOT set_pwm_to1/set_pwm_to1_D2); |
FTCPE_ct1: FTCPE port map (ct(1),ct(0),clk,'0','0'); |
FDCPE_ct2: FDCPE port map (ct(2),ct_D(2),clk,'0','0');
ct_D(2) <= ((ct(2) AND NOT XLXI_1/T3/XLXI_1/T3_D2) OR (ct(0) AND ct(1) AND NOT XLXI_1/T3/XLXI_1/T3_D2)); |
FDCPE_ct3: FDCPE port map (ct(3),ct_D(3),clk,'0','0');
ct_D(3) <= ((ct(3) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T3/XLXI_1/T3_D2) OR (NOT ct(3) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T3/XLXI_1/T3_D2)); |
FDCPE_ct4: FDCPE port map (ct(4),ct_D(4),clk,'0','0');
ct_D(4) <= ((ct(4) AND NOT XLXI_1/T5/XLXI_1/T5_D2) OR (ct(3) AND XLXI_1/T3/XLXI_1/T3_D2 AND NOT XLXI_1/T5/XLXI_1/T5_D2)); |
FDCPE_ct5: FDCPE port map (ct(5),ct_D(5),clk,'0','0');
ct_D(5) <= ((ct(5) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T5/XLXI_1/T5_D2) OR (NOT ct(5) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T5/XLXI_1/T5_D2)); |
FDCPE_ct6: FDCPE port map (ct(6),ct_D(6),clk,'0','0');
ct_D(6) <= ((ct(6) AND NOT XLXI_1/T7/XLXI_1/T7_D2) OR (ct(5) AND XLXI_1/T5/XLXI_1/T5_D2 AND NOT XLXI_1/T7/XLXI_1/T7_D2)); |
FDCPE_ct7: FDCPE port map (ct(7),ct_D(7),clk,'0','0');
ct_D(7) <= ((ct(7) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T7/XLXI_1/T7_D2) OR (NOT ct(7) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T7/XLXI_1/T7_D2)); |
FDCPE_ct8: FDCPE port map (ct(8),ct_D(8),clk,'0','0');
ct_D(8) <= ((ct(8) AND NOT XLXI_1/T9/XLXI_1/T9_D2) OR (ct(7) AND XLXI_1/T7/XLXI_1/T7_D2 AND NOT XLXI_1/T9/XLXI_1/T9_D2)); |
FDCPE_ct9: FDCPE port map (ct(9),ct_D(9),clk,'0','0');
ct_D(9) <= ((ct(9) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T9/XLXI_1/T9_D2) OR (NOT ct(9) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T9/XLXI_1/T9_D2)); |
FDCPE_ct10: FDCPE port map (ct(10),ct_D(10),clk,'0','0');
ct_D(10) <= ((ct(10) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T11/XLXI_1/T11_D2) OR (ct(9) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T9/XLXI_1/T9_D2 AND NOT XLXI_1/T11/XLXI_1/T11_D2)); |
FDCPE_ct11: FDCPE port map (ct(11),ct_D(11),clk,'0','0');
ct_D(11) <= ((ct(11) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T11/XLXI_1/T11_D2) OR (NOT ct(11) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T11/XLXI_1/T11_D2)); |
FDCPE_ct12: FDCPE port map (ct(12),ct_D(12),clk,'0','0');
ct_D(12) <= ((ct(12) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T13/XLXI_1/T13_D2) OR (ct(11) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T11/XLXI_1/T11_D2 AND NOT XLXI_1/T13/XLXI_1/T13_D2)); |
FDCPE_ct13: FDCPE port map (ct(13),ct_D(13),clk,'0','0');
ct_D(13) <= ((ct(13) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T13/XLXI_1/T13_D2) OR (NOT ct(13) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T13/XLXI_1/T13_D2)); |
FDCPE_ct14: FDCPE port map (ct(14),ct_D(14),clk,'0','0');
ct_D(14) <= ((ct(14) AND NOT XLXI_1/T15/XLXI_1/T15_D2) OR (ct(13) AND XLXI_1/T13/XLXI_1/T13_D2 AND NOT XLXI_1/T15/XLXI_1/T15_D2)); |
FDCPE_ct15: FDCPE port map (ct(15),ct_D(15),clk,'0','0');
ct_D(15) <= ((ct(15) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T15/XLXI_1/T15_D2) OR (NOT ct(15) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T15/XLXI_1/T15_D2)); |
FDCPE_out0: FDCPE port map (out0,out0_D,clk,'0','0');
out0_D <= ((EXP18_.EXP) OR (XLXN_26(5) AND out0 AND NOT ct(5)) OR (NOT XLXN_26(5) AND out0 AND ct(5)) OR (XLXN_26(6) AND out0 AND NOT ct(6)) OR (NOT XLXN_26(6) AND out0 AND ct(6)) OR (NOT XLXN_26(7) AND out0 AND ct(7)) OR (EXP21_.EXP) OR (XLXN_26(1) AND out0 AND NOT ct(1)) OR (NOT XLXN_26(1) AND out0 AND ct(1)) OR (XLXN_26(4) AND out0 AND NOT ct(4)) OR (NOT XLXN_26(4) AND out0 AND ct(4)) OR (XLXN_26(7) AND out0 AND NOT ct(7)) OR (NOT out0 AND set_pwm_to1/set_pwm_to1_D2) OR (XLXN_26(0) AND out0 AND NOT ct(0)) OR (NOT XLXN_26(0) AND out0 AND ct(0)) OR (XLXN_26(3) AND out0 AND NOT ct(3)) OR (NOT XLXN_26(3) AND out0 AND ct(3))); |
set_pwm_to1/set_pwm_to1_D2 <= (NOT ct(0) AND NOT ct(4) AND NOT ct(1) AND NOT ct(5) AND NOT ct(8) AND
NOT ct(12) AND NOT ct(2) AND NOT ct(6) AND ct(9) AND NOT ct(10) AND NOT ct(13) AND NOT ct(3) AND NOT ct(7) AND ct(11) AND NOT ct(14) AND NOT ct(15)); |
FDCPE_spi0: FDCPE port map (spi(0),spi_din,spi_clk,'0','0',spi_ce); |
FDCPE_spi1: FDCPE port map (spi(1),spi(0),spi_clk,'0','0',spi_ce); |
FDCPE_spi2: FDCPE port map (spi(2),spi(1),spi_clk,'0','0',spi_ce); |
FDCPE_spi3: FDCPE port map (spi(3),spi(2),spi_clk,'0','0',spi_ce); |
FDCPE_spi4: FDCPE port map (spi(4),spi(3),spi_clk,'0','0',spi_ce); |
FDCPE_spi5: FDCPE port map (spi(5),spi(4),spi_clk,'0','0',spi_ce); |
FDCPE_spi6: FDCPE port map (spi(6),spi(5),spi_clk,'0','0',spi_ce); |
FDCPE_spi7: FDCPE port map (spi(7),spi(6),spi_clk,'0','0',spi_ce); |
FDCPE_spi8: FDCPE port map (spi(8),spi(7),spi_clk,'0','0',spi_ce); |
FDCPE_spi9: FDCPE port map (spi(9),spi(8),spi_clk,'0','0',spi_ce); |
FDCPE_spi10: FDCPE port map (spi(10),spi(9),spi_clk,'0','0',spi_ce); |
FDCPE_spi11: FDCPE port map (spi(11),spi(10),spi_clk,'0','0',spi_ce); |
Register Legend:
FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); |