cpldfit: version O.61xd Xilinx Inc. Fitter Report Design Name: pwm_16x Date: 1-13-2013, 10:42PM Device Used: XC95288XL-10-TQ144 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 45 /288 ( 16%) 95 /1440 ( 7%) 79 /864 ( 9%) 37 /288 ( 13%) 5 /117 ( 4%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 13/18 15/54 21/90 0/ 8 FB2 18/18* 13/54 36/90 1/10 FB3 10/18 14/54 17/90 2/ 5 FB4 2/18 16/54 2/90 0/ 6 FB5 1/18 3/54 2/90 0/ 8 FB6 0/18 0/54 0/90 0/ 8 FB7 0/18 0/54 0/90 0/ 4 FB8 0/18 0/54 0/90 1/ 5 FB9 0/18 0/54 0/90 0/ 9 FB10 1/18 18/54 17/90 1/10 FB11 0/18 0/54 0/90 0/ 7 FB12 0/18 0/54 0/90 0/ 6 FB13 0/18 0/54 0/90 0/ 6 FB14 0/18 0/54 0/90 0/ 8 FB15 0/18 0/54 0/90 0/ 9 FB16 0/18 0/54 0/90 0/ 8 ----- ----- ----- ----- 45/288 79/864 95/1440 5/117 * - Resource is exhausted ** Global Control Resources ** Signal 'clk' mapped onto global clock net GCK1. Signal 'spi_clk' mapped onto global clock net GCK2. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 2 2 | I/O : 3 109 Output : 1 1 | GCK/IO : 2 3 Bidirectional : 0 0 | GTS/IO : 0 4 GCK : 2 2 | GSR/IO : 0 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 5 5 ** Power Data ** There are 45 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'pwm_16x.ise'. ************************* Summary of Mapped Logic ************************ ** 1 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State out0 17 18 FB10_5 119 I/O O STD FAST RESET ** 44 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State ct<1> 1 1 FB1_6 STD RESET ct<0> 1 2 FB1_7 STD RESET XLXI_1/T9/XLXI_1/T9_D2 1 3 FB1_8 STD XLXI_1/T7/XLXI_1/T7_D2 1 3 FB1_9 STD XLXI_1/T5/XLXI_1/T5_D2 1 3 FB1_10 STD ct<9> 2 3 FB1_11 STD RESET ct<8> 2 4 FB1_12 STD RESET ct<7> 2 3 FB1_13 STD RESET ct<6> 2 4 FB1_14 STD RESET ct<5> 2 3 FB1_15 STD RESET ct<4> 2 4 FB1_16 STD RESET ct<3> 2 3 FB1_17 STD RESET ct<2> 2 4 FB1_18 STD RESET spi<9> 2 2 FB2_1 STD RESET spi<8> 2 2 FB2_2 STD RESET spi<6> 2 2 FB2_3 STD RESET spi<5> 2 2 FB2_4 STD RESET spi<4> 2 2 FB2_5 STD RESET spi<3> 2 2 FB2_6 STD RESET spi<2> 2 2 FB2_7 STD RESET spi<1> 2 2 FB2_8 STD RESET spi<11> 2 2 FB2_9 STD RESET spi<10> 2 2 FB2_10 STD RESET XLXN_26<7> 2 6 FB2_11 STD RESET XLXN_26<6> 2 6 FB2_12 STD RESET XLXN_26<5> 2 6 FB2_13 STD RESET XLXN_26<4> 2 6 FB2_14 STD RESET XLXN_26<3> 2 6 FB2_15 STD RESET XLXN_26<2> 2 6 FB2_16 STD RESET XLXN_26<1> 2 6 FB2_17 STD RESET XLXN_26<0> 2 6 FB2_18 STD RESET XLXI_1/T15/XLXI_1/T15_D2 1 3 FB3_9 STD XLXI_1/T13/XLXI_1/T13_D2 1 3 FB3_10 STD XLXI_1/T11/XLXI_1/T11_D2 1 3 FB3_11 STD spi<7> 2 2 FB3_12 STD RESET spi<0> 2 2 FB3_13 STD RESET ct<14> 2 4 FB3_14 STD RESET ct<13> 2 3 FB3_15 STD RESET ct<12> 2 5 FB3_16 STD RESET ct<11> 2 3 FB3_17 STD RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State ct<10> 2 5 FB3_18 STD RESET set_pwm_to1/set_pwm_to1_D2 1 16 FB4_17 STD XLXI_1/T3/XLXI_1/T3_D2 1 3 FB4_18 STD ct<15> 2 3 FB5_18 STD RESET ** 4 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use spi_din FB2_3 10 I/O I clk FB3_10 30~ GCK/I/O GCK spi_clk FB3_14 32~ GCK/I/O GCK spi_ce FB8_5 132 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 15/39 Number of signals used by logic mapping into function block: 15 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 (b) (unused) 0 0 0 5 FB1_2 (b) (unused) 0 0 0 5 FB1_3 (b) (unused) 0 0 0 5 FB1_4 (b) (unused) 0 0 0 5 FB1_5 20 I/O ct<1> 1 0 0 4 FB1_6 21 I/O (b) ct<0> 1 0 0 4 FB1_7 (b) (b) XLXI_1/T9/XLXI_1/T9_D2 1 0 0 4 FB1_8 22 I/O (b) XLXI_1/T7/XLXI_1/T7_D2 1 0 0 4 FB1_9 (b) (b) XLXI_1/T5/XLXI_1/T5_D2 1 0 0 4 FB1_10 23 I/O (b) ct<9> 2 0 0 3 FB1_11 (b) (b) ct<8> 2 0 0 3 FB1_12 24 I/O (b) ct<7> 2 0 0 3 FB1_13 (b) (b) ct<6> 2 0 0 3 FB1_14 25 I/O (b) ct<5> 2 0 0 3 FB1_15 26 I/O (b) ct<4> 2 0 0 3 FB1_16 (b) (b) ct<3> 2 0 0 3 FB1_17 27 I/O (b) ct<2> 2 0 0 3 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: XLXI_1/T3/XLXI_1/T3_D2 6: ct<1> 11: ct<6> 2: XLXI_1/T5/XLXI_1/T5_D2 7: ct<2> 12: ct<7> 3: XLXI_1/T7/XLXI_1/T7_D2 8: ct<3> 13: ct<8> 4: XLXI_1/T9/XLXI_1/T9_D2 9: ct<4> 14: ct<9> 5: ct<0> 10: ct<5> 15: set_pwm_to1/set_pwm_to1_D2 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs ct<1> ....X................................... 1 ct<0> ....X.........X......................... 2 XLXI_1/T9/XLXI_1/T9_D2 ..X........XX........................... 3 XLXI_1/T7/XLXI_1/T7_D2 .X.......XX............................. 3 XLXI_1/T5/XLXI_1/T5_D2 X......XX............................... 3 ct<9> ...X.........XX......................... 3 ct<8> ..XX.......XX........................... 4 ct<7> ..X........X..X......................... 3 ct<6> .XX......XX............................. 4 ct<5> .X.......X....X......................... 3 ct<4> XX.....XX............................... 4 ct<3> X......X......X......................... 3 ct<2> X...XXX................................. 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 13/41 Number of signals used by logic mapping into function block: 13 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use spi<9> 2 0 0 3 FB2_1 (b) (b) spi<8> 2 0 0 3 FB2_2 9 I/O (b) spi<6> 2 0 0 3 FB2_3 10 I/O I spi<5> 2 0 0 3 FB2_4 (b) (b) spi<4> 2 0 0 3 FB2_5 11 I/O (b) spi<3> 2 0 0 3 FB2_6 12 I/O (b) spi<2> 2 0 0 3 FB2_7 (b) (b) spi<1> 2 0 0 3 FB2_8 13 I/O (b) spi<11> 2 0 0 3 FB2_9 (b) (b) spi<10> 2 0 0 3 FB2_10 14 I/O (b) XLXN_26<7> 2 0 0 3 FB2_11 (b) (b) XLXN_26<6> 2 0 0 3 FB2_12 15 I/O (b) XLXN_26<5> 2 0 0 3 FB2_13 (b) (b) XLXN_26<4> 2 0 0 3 FB2_14 16 I/O (b) XLXN_26<3> 2 0 0 3 FB2_15 17 I/O (b) XLXN_26<2> 2 0 0 3 FB2_16 (b) (b) XLXN_26<1> 2 0 0 3 FB2_17 19 I/O (b) XLXN_26<0> 2 0 0 3 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: spi<0> 6: spi<3> 10: spi<7> 2: spi<10> 7: spi<4> 11: spi<8> 3: spi<11> 8: spi<5> 12: spi<9> 4: spi<1> 9: spi<6> 13: spi_ce 5: spi<2> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs spi<9> ..........X.X........................... 2 spi<8> .........X..X........................... 2 spi<6> .......X....X........................... 2 spi<5> ......X.....X........................... 2 spi<4> .....X......X........................... 2 spi<3> ....X.......X........................... 2 spi<2> ...X........X........................... 2 spi<1> X...........X........................... 2 spi<11> .X..........X........................... 2 spi<10> ...........XX........................... 2 XLXN_26<7> .XX......XXXX........................... 6 XLXN_26<6> .XX.....X.XXX........................... 6 XLXN_26<5> .XX....X..XXX........................... 6 XLXN_26<4> .XX...X...XXX........................... 6 XLXN_26<3> .XX..X....XXX........................... 6 XLXN_26<2> .XX.X.....XXX........................... 6 XLXN_26<1> .XXX......XXX........................... 6 XLXN_26<0> XXX.......XXX........................... 6 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 14/40 Number of signals used by logic mapping into function block: 14 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB3_1 (b) (unused) 0 0 0 5 FB3_2 28 I/O (unused) 0 0 0 5 FB3_3 (b) (unused) 0 0 0 5 FB3_4 (b) (unused) 0 0 0 5 FB3_5 (b) (unused) 0 0 0 5 FB3_6 (b) (unused) 0 0 0 5 FB3_7 (b) (unused) 0 0 0 5 FB3_8 (b) XLXI_1/T15/XLXI_1/T15_D2 1 0 0 4 FB3_9 (b) (b) XLXI_1/T13/XLXI_1/T13_D2 1 0 0 4 FB3_10 30 GCK/I/O GCK XLXI_1/T11/XLXI_1/T11_D2 1 0 0 4 FB3_11 (b) (b) spi<7> 2 0 0 3 FB3_12 31 I/O (b) spi<0> 2 0 0 3 FB3_13 (b) (b) ct<14> 2 0 0 3 FB3_14 32 GCK/I/O GCK ct<13> 2 0 0 3 FB3_15 33 I/O (b) ct<12> 2 0 0 3 FB3_16 (b) (b) ct<11> 2 0 0 3 FB3_17 (b) (b) ct<10> 2 0 0 3 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: XLXI_1/T11/XLXI_1/T11_D2 6: ct<11> 11: set_pwm_to1/set_pwm_to1_D2 2: XLXI_1/T13/XLXI_1/T13_D2 7: ct<12> 12: spi<6> 3: XLXI_1/T15/XLXI_1/T15_D2 8: ct<13> 13: spi_ce 4: XLXI_1/T9/XLXI_1/T9_D2 9: ct<14> 14: spi_din 5: ct<10> 10: ct<9> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs XLXI_1/T15/XLXI_1/T15_D2 .X.....XX............................... 3 XLXI_1/T13/XLXI_1/T13_D2 X....XX................................. 3 XLXI_1/T11/XLXI_1/T11_D2 ...XX....X.............................. 3 spi<7> ...........XX........................... 2 spi<0> ............XX.......................... 2 ct<14> .XX....XX............................... 4 ct<13> .X.....X..X............................. 3 ct<12> XX...XX...X............................. 5 ct<11> X....X....X............................. 3 ct<10> X..XX....XX............................. 5 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 16/38 Number of signals used by logic mapping into function block: 16 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB4_1 (b) (unused) 0 0 0 5 FB4_2 2 GTS/I/O (unused) 0 0 0 5 FB4_3 (b) (unused) 0 0 0 5 FB4_4 (b) (unused) 0 0 0 5 FB4_5 3 GTS/I/O (unused) 0 0 0 5 FB4_6 4 I/O (unused) 0 0 0 5 FB4_7 (b) (unused) 0 0 0 5 FB4_8 5 GTS/I/O (unused) 0 0 0 5 FB4_9 (b) (unused) 0 0 0 5 FB4_10 (b) (unused) 0 0 0 5 FB4_11 (b) (unused) 0 0 0 5 FB4_12 6 GTS/I/O (unused) 0 0 0 5 FB4_13 (b) (unused) 0 0 0 5 FB4_14 7 I/O (unused) 0 0 0 5 FB4_15 (b) (unused) 0 0 0 5 FB4_16 (b) set_pwm_to1/set_pwm_to1_D2 1 0 0 4 FB4_17 (b) (b) XLXI_1/T3/XLXI_1/T3_D2 1 0 0 4 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: ct<0> 7: ct<15> 12: ct<5> 2: ct<10> 8: ct<1> 13: ct<6> 3: ct<11> 9: ct<2> 14: ct<7> 4: ct<12> 10: ct<3> 15: ct<8> 5: ct<13> 11: ct<4> 16: ct<9> 6: ct<14> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs set_pwm_to1/set_pwm_to1_D2 XXXXXXXXXXXXXXXX........................ 16 XLXI_1/T3/XLXI_1/T3_D2 X......XX............................... 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 3/51 Number of signals used by logic mapping into function block: 3 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB5_1 (b) (unused) 0 0 0 5 FB5_2 34 I/O (unused) 0 0 0 5 FB5_3 (b) (unused) 0 0 0 5 FB5_4 (b) (unused) 0 0 0 5 FB5_5 35 I/O (unused) 0 0 0 5 FB5_6 (b) (unused) 0 0 0 5 FB5_7 (b) (unused) 0 0 0 5 FB5_8 38 GCK/I/O (unused) 0 0 0 5 FB5_9 (b) (unused) 0 0 0 5 FB5_10 39 I/O (unused) 0 0 0 5 FB5_11 (b) (unused) 0 0 0 5 FB5_12 40 I/O (unused) 0 0 0 5 FB5_13 (b) (unused) 0 0 0 5 FB5_14 41 I/O (unused) 0 0 0 5 FB5_15 43 I/O (unused) 0 0 0 5 FB5_16 (b) (unused) 0 0 0 5 FB5_17 44 I/O ct<15> 2 0 0 3 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: XLXI_1/T15/XLXI_1/T15_D2 2: ct<15> 3: set_pwm_to1/set_pwm_to1_D2 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs ct<15> XXX..................................... 3 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB6_1 (b) (unused) 0 0 0 5 FB6_2 135 I/O (unused) 0 0 0 5 FB6_3 136 I/O (unused) 0 0 0 5 FB6_4 (b) (unused) 0 0 0 5 FB6_5 137 I/O (unused) 0 0 0 5 FB6_6 138 I/O (unused) 0 0 0 5 FB6_7 (b) (unused) 0 0 0 5 FB6_8 139 I/O (unused) 0 0 0 5 FB6_9 (b) (unused) 0 0 0 5 FB6_10 140 I/O (unused) 0 0 0 5 FB6_11 (b) (unused) 0 0 0 5 FB6_12 (b) (unused) 0 0 0 5 FB6_13 (b) (unused) 0 0 0 5 FB6_14 142 I/O (unused) 0 0 0 5 FB6_15 143 GSR/I/O (unused) 0 0 0 5 FB6_16 (b) (unused) 0 0 0 5 FB6_17 (b) (unused) 0 0 0 5 FB6_18 (b) *********************************** FB7 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB7_1 (b) (unused) 0 0 0 5 FB7_2 (b) (unused) 0 0 0 5 FB7_3 45 I/O (unused) 0 0 0 5 FB7_4 (b) (unused) 0 0 0 5 FB7_5 46 I/O (unused) 0 0 0 5 FB7_6 (b) (unused) 0 0 0 5 FB7_7 (b) (unused) 0 0 0 5 FB7_8 (b) (unused) 0 0 0 5 FB7_9 (b) (unused) 0 0 0 5 FB7_10 (b) (unused) 0 0 0 5 FB7_11 (b) (unused) 0 0 0 5 FB7_12 48 I/O (unused) 0 0 0 5 FB7_13 (b) (unused) 0 0 0 5 FB7_14 (b) (unused) 0 0 0 5 FB7_15 49 I/O (unused) 0 0 0 5 FB7_16 (b) (unused) 0 0 0 5 FB7_17 (b) (unused) 0 0 0 5 FB7_18 (b) *********************************** FB8 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB8_1 (b) (unused) 0 0 0 5 FB8_2 130 I/O (unused) 0 0 0 5 FB8_3 131 I/O (unused) 0 0 0 5 FB8_4 (b) (unused) 0 0 0 5 FB8_5 132 I/O I (unused) 0 0 0 5 FB8_6 (b) (unused) 0 0 0 5 FB8_7 (b) (unused) 0 0 0 5 FB8_8 133 I/O (unused) 0 0 0 5 FB8_9 (b) (unused) 0 0 0 5 FB8_10 134 I/O (unused) 0 0 0 5 FB8_11 (b) (unused) 0 0 0 5 FB8_12 (b) (unused) 0 0 0 5 FB8_13 (b) (unused) 0 0 0 5 FB8_14 (b) (unused) 0 0 0 5 FB8_15 (b) (unused) 0 0 0 5 FB8_16 (b) (unused) 0 0 0 5 FB8_17 (b) (unused) 0 0 0 5 FB8_18 (b) *********************************** FB9 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB9_1 (b) (unused) 0 0 0 5 FB9_2 50 I/O (unused) 0 0 0 5 FB9_3 51 I/O (unused) 0 0 0 5 FB9_4 (b) (unused) 0 0 0 5 FB9_5 52 I/O (unused) 0 0 0 5 FB9_6 53 I/O (unused) 0 0 0 5 FB9_7 (b) (unused) 0 0 0 5 FB9_8 54 I/O (unused) 0 0 0 5 FB9_9 (b) (unused) 0 0 0 5 FB9_10 (b) (unused) 0 0 0 5 FB9_11 56 I/O (unused) 0 0 0 5 FB9_12 57 I/O (unused) 0 0 0 5 FB9_13 (b) (unused) 0 0 0 5 FB9_14 58 I/O (unused) 0 0 0 5 FB9_15 (b) (unused) 0 0 0 5 FB9_16 (b) (unused) 0 0 0 5 FB9_17 59 I/O (unused) 0 0 0 5 FB9_18 (b) *********************************** FB10 *********************************** Number of function block inputs used/remaining: 18/36 Number of signals used by logic mapping into function block: 18 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB10_1 (b) (unused) 0 0 0 5 FB10_2 117 I/O (unused) 0 0 \/1 4 FB10_3 118 I/O (b) (unused) 0 0 \/5 0 FB10_4 (b) (b) out0 17 12<- 0 0 FB10_5 119 I/O O (unused) 0 0 /\5 0 FB10_6 120 I/O (b) (unused) 0 0 /\1 4 FB10_7 (b) (b) (unused) 0 0 0 5 FB10_8 121 I/O (unused) 0 0 0 5 FB10_9 (b) (unused) 0 0 0 5 FB10_10 124 I/O (unused) 0 0 0 5 FB10_11 125 I/O (unused) 0 0 0 5 FB10_12 126 I/O (unused) 0 0 0 5 FB10_13 (b) (unused) 0 0 0 5 FB10_14 128 I/O (unused) 0 0 0 5 FB10_15 (b) (unused) 0 0 0 5 FB10_16 (b) (unused) 0 0 0 5 FB10_17 129 I/O (unused) 0 0 0 5 FB10_18 (b) Signals Used by Logic in Function Block 1: XLXN_26<0> 7: XLXN_26<6> 13: ct<4> 2: XLXN_26<1> 8: XLXN_26<7> 14: ct<5> 3: XLXN_26<2> 9: ct<0> 15: ct<6> 4: XLXN_26<3> 10: ct<1> 16: ct<7> 5: XLXN_26<4> 11: ct<2> 17: out0 6: XLXN_26<5> 12: ct<3> 18: set_pwm_to1/set_pwm_to1_D2 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs out0 XXXXXXXXXXXXXXXXXX...................... 18 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB11 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB11_1 (b) (unused) 0 0 0 5 FB11_2 (b) (unused) 0 0 0 5 FB11_3 60 I/O (unused) 0 0 0 5 FB11_4 (b) (unused) 0 0 0 5 FB11_5 61 I/O (unused) 0 0 0 5 FB11_6 (b) (unused) 0 0 0 5 FB11_7 (b) (unused) 0 0 0 5 FB11_8 (b) (unused) 0 0 0 5 FB11_9 (b) (unused) 0 0 0 5 FB11_10 64 I/O (unused) 0 0 0 5 FB11_11 66 I/O (unused) 0 0 0 5 FB11_12 68 I/O (unused) 0 0 0 5 FB11_13 (b) (unused) 0 0 0 5 FB11_14 69 I/O (unused) 0 0 0 5 FB11_15 (b) (unused) 0 0 0 5 FB11_16 (b) (unused) 0 0 0 5 FB11_17 70 I/O (unused) 0 0 0 5 FB11_18 (b) *********************************** FB12 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB12_1 (b) (unused) 0 0 0 5 FB12_2 110 I/O (unused) 0 0 0 5 FB12_3 111 I/O (unused) 0 0 0 5 FB12_4 (b) (unused) 0 0 0 5 FB12_5 112 I/O (unused) 0 0 0 5 FB12_6 (b) (unused) 0 0 0 5 FB12_7 (b) (unused) 0 0 0 5 FB12_8 113 I/O (unused) 0 0 0 5 FB12_9 (b) (unused) 0 0 0 5 FB12_10 115 I/O (unused) 0 0 0 5 FB12_11 (b) (unused) 0 0 0 5 FB12_12 116 I/O (unused) 0 0 0 5 FB12_13 (b) (unused) 0 0 0 5 FB12_14 (b) (unused) 0 0 0 5 FB12_15 (b) (unused) 0 0 0 5 FB12_16 (b) (unused) 0 0 0 5 FB12_17 (b) (unused) 0 0 0 5 FB12_18 (b) *********************************** FB13 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB13_1 (b) (unused) 0 0 0 5 FB13_2 71 I/O (unused) 0 0 0 5 FB13_3 (b) (unused) 0 0 0 5 FB13_4 (b) (unused) 0 0 0 5 FB13_5 (b) (unused) 0 0 0 5 FB13_6 (b) (unused) 0 0 0 5 FB13_7 (b) (unused) 0 0 0 5 FB13_8 74 I/O (unused) 0 0 0 5 FB13_9 (b) (unused) 0 0 0 5 FB13_10 (b) (unused) 0 0 0 5 FB13_11 75 I/O (unused) 0 0 0 5 FB13_12 (b) (unused) 0 0 0 5 FB13_13 (b) (unused) 0 0 0 5 FB13_14 76 I/O (unused) 0 0 0 5 FB13_15 77 I/O (unused) 0 0 0 5 FB13_16 (b) (unused) 0 0 0 5 FB13_17 78 I/O (unused) 0 0 0 5 FB13_18 (b) *********************************** FB14 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB14_1 (b) (unused) 0 0 0 5 FB14_2 (b) (unused) 0 0 0 5 FB14_3 100 I/O (unused) 0 0 0 5 FB14_4 (b) (unused) 0 0 0 5 FB14_5 101 I/O (unused) 0 0 0 5 FB14_6 102 I/O (unused) 0 0 0 5 FB14_7 (b) (unused) 0 0 0 5 FB14_8 103 I/O (unused) 0 0 0 5 FB14_9 (b) (unused) 0 0 0 5 FB14_10 104 I/O (unused) 0 0 0 5 FB14_11 105 I/O (unused) 0 0 0 5 FB14_12 (b) (unused) 0 0 0 5 FB14_13 (b) (unused) 0 0 0 5 FB14_14 106 I/O (unused) 0 0 0 5 FB14_15 107 I/O (unused) 0 0 0 5 FB14_16 (b) (unused) 0 0 0 5 FB14_17 (b) (unused) 0 0 0 5 FB14_18 (b) *********************************** FB15 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB15_1 (b) (unused) 0 0 0 5 FB15_2 79 I/O (unused) 0 0 0 5 FB15_3 80 I/O (unused) 0 0 0 5 FB15_4 (b) (unused) 0 0 0 5 FB15_5 (b) (unused) 0 0 0 5 FB15_6 (b) (unused) 0 0 0 5 FB15_7 (b) (unused) 0 0 0 5 FB15_8 81 I/O (unused) 0 0 0 5 FB15_9 (b) (unused) 0 0 0 5 FB15_10 82 I/O (unused) 0 0 0 5 FB15_11 83 I/O (unused) 0 0 0 5 FB15_12 85 I/O (unused) 0 0 0 5 FB15_13 (b) (unused) 0 0 0 5 FB15_14 86 I/O (unused) 0 0 0 5 FB15_15 87 I/O (unused) 0 0 0 5 FB15_16 (b) (unused) 0 0 0 5 FB15_17 88 I/O (unused) 0 0 0 5 FB15_18 (b) *********************************** FB16 *********************************** Number of function block inputs used/remaining: 0/54 Number of signals used by logic mapping into function block: 0 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB16_1 (b) (unused) 0 0 0 5 FB16_2 91 I/O (unused) 0 0 0 5 FB16_3 92 I/O (unused) 0 0 0 5 FB16_4 (b) (unused) 0 0 0 5 FB16_5 93 I/O (unused) 0 0 0 5 FB16_6 94 I/O (unused) 0 0 0 5 FB16_7 (b) (unused) 0 0 0 5 FB16_8 95 I/O (unused) 0 0 0 5 FB16_9 (b) (unused) 0 0 0 5 FB16_10 96 I/O (unused) 0 0 0 5 FB16_11 97 I/O (unused) 0 0 0 5 FB16_12 98 I/O (unused) 0 0 0 5 FB16_13 (b) (unused) 0 0 0 5 FB16_14 (b) (unused) 0 0 0 5 FB16_15 (b) (unused) 0 0 0 5 FB16_16 (b) (unused) 0 0 0 5 FB16_17 (b) (unused) 0 0 0 5 FB16_18 (b) ******************************* Equations ******************************** ********** Mapped Logic ********** XLXI_1/T11/XLXI_1/T11_D2 <= (ct(9) AND ct(10) AND XLXI_1/T9/XLXI_1/T9_D2); XLXI_1/T13/XLXI_1/T13_D2 <= (ct(12) AND ct(11) AND XLXI_1/T11/XLXI_1/T11_D2); XLXI_1/T15/XLXI_1/T15_D2 <= (ct(13) AND ct(14) AND XLXI_1/T13/XLXI_1/T13_D2); XLXI_1/T3/XLXI_1/T3_D2 <= (ct(0) AND ct(1) AND ct(2)); XLXI_1/T5/XLXI_1/T5_D2 <= (ct(4) AND ct(3) AND XLXI_1/T3/XLXI_1/T3_D2); XLXI_1/T7/XLXI_1/T7_D2 <= (ct(5) AND ct(6) AND XLXI_1/T5/XLXI_1/T5_D2); XLXI_1/T9/XLXI_1/T9_D2 <= (ct(8) AND ct(7) AND XLXI_1/T7/XLXI_1/T7_D2); FDCPE_XLXN_260: FDCPE port map (XLXN_26(0),spi(0),spi_clk,'0','0',XLXN_26_CE(0)); XLXN_26_CE(0) <= (NOT spi_ce AND NOT spi(10) AND NOT spi(8) AND NOT spi(9) AND NOT spi(11)); FDCPE_XLXN_261: FDCPE port map (XLXN_26(1),spi(1),spi_clk,'0','0',XLXN_26_CE(1)); XLXN_26_CE(1) <= (NOT spi_ce AND NOT spi(10) AND NOT spi(8) AND NOT spi(9) AND NOT spi(11)); FDCPE_XLXN_262: FDCPE port map (XLXN_26(2),spi(2),spi_clk,'0','0',XLXN_26_CE(2)); XLXN_26_CE(2) <= (NOT spi_ce AND NOT spi(10) AND NOT spi(8) AND NOT spi(9) AND NOT spi(11)); FDCPE_XLXN_263: FDCPE port map (XLXN_26(3),spi(3),spi_clk,'0','0',XLXN_26_CE(3)); XLXN_26_CE(3) <= (NOT spi_ce AND NOT spi(10) AND NOT spi(8) AND NOT spi(9) AND NOT spi(11)); FDCPE_XLXN_264: FDCPE port map (XLXN_26(4),spi(4),spi_clk,'0','0',XLXN_26_CE(4)); XLXN_26_CE(4) <= (NOT spi_ce AND NOT spi(10) AND NOT spi(8) AND NOT spi(9) AND NOT spi(11)); FDCPE_XLXN_265: FDCPE port map (XLXN_26(5),spi(5),spi_clk,'0','0',XLXN_26_CE(5)); XLXN_26_CE(5) <= (NOT spi_ce AND NOT spi(10) AND NOT spi(8) AND NOT spi(9) AND NOT spi(11)); FDCPE_XLXN_266: FDCPE port map (XLXN_26(6),spi(6),spi_clk,'0','0',XLXN_26_CE(6)); XLXN_26_CE(6) <= (NOT spi_ce AND NOT spi(10) AND NOT spi(8) AND NOT spi(9) AND NOT spi(11)); FDCPE_XLXN_267: FDCPE port map (XLXN_26(7),spi(7),spi_clk,'0','0',XLXN_26_CE(7)); XLXN_26_CE(7) <= (NOT spi_ce AND NOT spi(10) AND NOT spi(8) AND NOT spi(9) AND NOT spi(11)); FDCPE_ct0: FDCPE port map (ct(0),ct_D(0),clk,'0','0'); ct_D(0) <= (NOT ct(0) AND NOT set_pwm_to1/set_pwm_to1_D2); FTCPE_ct1: FTCPE port map (ct(1),ct(0),clk,'0','0'); FDCPE_ct2: FDCPE port map (ct(2),ct_D(2),clk,'0','0'); ct_D(2) <= ((ct(2) AND NOT XLXI_1/T3/XLXI_1/T3_D2) OR (ct(0) AND ct(1) AND NOT XLXI_1/T3/XLXI_1/T3_D2)); FDCPE_ct3: FDCPE port map (ct(3),ct_D(3),clk,'0','0'); ct_D(3) <= ((ct(3) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T3/XLXI_1/T3_D2) OR (NOT ct(3) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T3/XLXI_1/T3_D2)); FDCPE_ct4: FDCPE port map (ct(4),ct_D(4),clk,'0','0'); ct_D(4) <= ((ct(4) AND NOT XLXI_1/T5/XLXI_1/T5_D2) OR (ct(3) AND XLXI_1/T3/XLXI_1/T3_D2 AND NOT XLXI_1/T5/XLXI_1/T5_D2)); FDCPE_ct5: FDCPE port map (ct(5),ct_D(5),clk,'0','0'); ct_D(5) <= ((ct(5) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T5/XLXI_1/T5_D2) OR (NOT ct(5) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T5/XLXI_1/T5_D2)); FDCPE_ct6: FDCPE port map (ct(6),ct_D(6),clk,'0','0'); ct_D(6) <= ((ct(6) AND NOT XLXI_1/T7/XLXI_1/T7_D2) OR (ct(5) AND XLXI_1/T5/XLXI_1/T5_D2 AND NOT XLXI_1/T7/XLXI_1/T7_D2)); FDCPE_ct7: FDCPE port map (ct(7),ct_D(7),clk,'0','0'); ct_D(7) <= ((ct(7) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T7/XLXI_1/T7_D2) OR (NOT ct(7) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T7/XLXI_1/T7_D2)); FDCPE_ct8: FDCPE port map (ct(8),ct_D(8),clk,'0','0'); ct_D(8) <= ((ct(8) AND NOT XLXI_1/T9/XLXI_1/T9_D2) OR (ct(7) AND XLXI_1/T7/XLXI_1/T7_D2 AND NOT XLXI_1/T9/XLXI_1/T9_D2)); FDCPE_ct9: FDCPE port map (ct(9),ct_D(9),clk,'0','0'); ct_D(9) <= ((ct(9) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T9/XLXI_1/T9_D2) OR (NOT ct(9) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T9/XLXI_1/T9_D2)); FDCPE_ct10: FDCPE port map (ct(10),ct_D(10),clk,'0','0'); ct_D(10) <= ((ct(10) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T11/XLXI_1/T11_D2) OR (ct(9) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T9/XLXI_1/T9_D2 AND NOT XLXI_1/T11/XLXI_1/T11_D2)); FDCPE_ct11: FDCPE port map (ct(11),ct_D(11),clk,'0','0'); ct_D(11) <= ((ct(11) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T11/XLXI_1/T11_D2) OR (NOT ct(11) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T11/XLXI_1/T11_D2)); FDCPE_ct12: FDCPE port map (ct(12),ct_D(12),clk,'0','0'); ct_D(12) <= ((ct(12) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T13/XLXI_1/T13_D2) OR (ct(11) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T11/XLXI_1/T11_D2 AND NOT XLXI_1/T13/XLXI_1/T13_D2)); FDCPE_ct13: FDCPE port map (ct(13),ct_D(13),clk,'0','0'); ct_D(13) <= ((ct(13) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T13/XLXI_1/T13_D2) OR (NOT ct(13) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T13/XLXI_1/T13_D2)); FDCPE_ct14: FDCPE port map (ct(14),ct_D(14),clk,'0','0'); ct_D(14) <= ((ct(14) AND NOT XLXI_1/T15/XLXI_1/T15_D2) OR (ct(13) AND XLXI_1/T13/XLXI_1/T13_D2 AND NOT XLXI_1/T15/XLXI_1/T15_D2)); FDCPE_ct15: FDCPE port map (ct(15),ct_D(15),clk,'0','0'); ct_D(15) <= ((ct(15) AND NOT set_pwm_to1/set_pwm_to1_D2 AND NOT XLXI_1/T15/XLXI_1/T15_D2) OR (NOT ct(15) AND NOT set_pwm_to1/set_pwm_to1_D2 AND XLXI_1/T15/XLXI_1/T15_D2)); FDCPE_out0: FDCPE port map (out0,out0_D,clk,'0','0'); out0_D <= ((EXP18_.EXP) OR (XLXN_26(5) AND out0 AND NOT ct(5)) OR (NOT XLXN_26(5) AND out0 AND ct(5)) OR (XLXN_26(6) AND out0 AND NOT ct(6)) OR (NOT XLXN_26(6) AND out0 AND ct(6)) OR (NOT XLXN_26(7) AND out0 AND ct(7)) OR (EXP21_.EXP) OR (XLXN_26(1) AND out0 AND NOT ct(1)) OR (NOT XLXN_26(1) AND out0 AND ct(1)) OR (XLXN_26(4) AND out0 AND NOT ct(4)) OR (NOT XLXN_26(4) AND out0 AND ct(4)) OR (XLXN_26(7) AND out0 AND NOT ct(7)) OR (NOT out0 AND set_pwm_to1/set_pwm_to1_D2) OR (XLXN_26(0) AND out0 AND NOT ct(0)) OR (NOT XLXN_26(0) AND out0 AND ct(0)) OR (XLXN_26(3) AND out0 AND NOT ct(3)) OR (NOT XLXN_26(3) AND out0 AND ct(3))); set_pwm_to1/set_pwm_to1_D2 <= (NOT ct(0) AND NOT ct(4) AND NOT ct(1) AND NOT ct(5) AND NOT ct(8) AND NOT ct(12) AND NOT ct(2) AND NOT ct(6) AND ct(9) AND NOT ct(10) AND NOT ct(13) AND NOT ct(3) AND NOT ct(7) AND ct(11) AND NOT ct(14) AND NOT ct(15)); FDCPE_spi0: FDCPE port map (spi(0),spi_din,spi_clk,'0','0',spi_ce); FDCPE_spi1: FDCPE port map (spi(1),spi(0),spi_clk,'0','0',spi_ce); FDCPE_spi2: FDCPE port map (spi(2),spi(1),spi_clk,'0','0',spi_ce); FDCPE_spi3: FDCPE port map (spi(3),spi(2),spi_clk,'0','0',spi_ce); FDCPE_spi4: FDCPE port map (spi(4),spi(3),spi_clk,'0','0',spi_ce); FDCPE_spi5: FDCPE port map (spi(5),spi(4),spi_clk,'0','0',spi_ce); FDCPE_spi6: FDCPE port map (spi(6),spi(5),spi_clk,'0','0',spi_ce); FDCPE_spi7: FDCPE port map (spi(7),spi(6),spi_clk,'0','0',spi_ce); FDCPE_spi8: FDCPE port map (spi(8),spi(7),spi_clk,'0','0',spi_ce); FDCPE_spi9: FDCPE port map (spi(9),spi(8),spi_clk,'0','0',spi_ce); FDCPE_spi10: FDCPE port map (spi(10),spi(9),spi_clk,'0','0',spi_ce); FDCPE_spi11: FDCPE port map (spi(11),spi(10),spi_clk,'0','0',spi_ce); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95288XL-10-TQ144 Pin Signal Pin Signal No. Name No. Name 1 VCC 73 VCC 2 KPR 74 KPR 3 KPR 75 KPR 4 KPR 76 KPR 5 KPR 77 KPR 6 KPR 78 KPR 7 KPR 79 KPR 8 VCC 80 KPR 9 KPR 81 KPR 10 spi_din 82 KPR 11 KPR 83 KPR 12 KPR 84 VCC 13 KPR 85 KPR 14 KPR 86 KPR 15 KPR 87 KPR 16 KPR 88 KPR 17 KPR 89 GND 18 GND 90 GND 19 KPR 91 KPR 20 KPR 92 KPR 21 KPR 93 KPR 22 KPR 94 KPR 23 KPR 95 KPR 24 KPR 96 KPR 25 KPR 97 KPR 26 KPR 98 KPR 27 KPR 99 GND 28 KPR 100 KPR 29 GND 101 KPR 30 clk 102 KPR 31 KPR 103 KPR 32 spi_clk 104 KPR 33 KPR 105 KPR 34 KPR 106 KPR 35 KPR 107 KPR 36 GND 108 GND 37 VCC 109 VCC 38 KPR 110 KPR 39 KPR 111 KPR 40 KPR 112 KPR 41 KPR 113 KPR 42 VCC 114 GND 43 KPR 115 KPR 44 KPR 116 KPR 45 KPR 117 KPR 46 KPR 118 KPR 47 GND 119 out0 48 KPR 120 KPR 49 KPR 121 KPR 50 KPR 122 TDO 51 KPR 123 GND 52 KPR 124 KPR 53 KPR 125 KPR 54 KPR 126 KPR 55 VCC 127 VCC 56 KPR 128 KPR 57 KPR 129 KPR 58 KPR 130 KPR 59 KPR 131 KPR 60 KPR 132 spi_ce 61 KPR 133 KPR 62 GND 134 KPR 63 TDI 135 KPR 64 KPR 136 KPR 65 TMS 137 KPR 66 KPR 138 KPR 67 TCK 139 KPR 68 KPR 140 KPR 69 KPR 141 VCC 70 KPR 142 KPR 71 KPR 143 KPR 72 GND 144 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95288xl-10-TQ144 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 54 Pterm Limit : 25